In testing a semiconductor device by a semiconductor test system, a semiconductor device under test is provided with various test signals with varying timings. The semiconductor test system must generate the test signals while accurately controlling timings of the test signals. Such timing differences are produced by delay circuits typically formed of CMOS circuits.
Such a delay circuit formed of CMOS circuits usually includes a series of CMOS gates, typically inverters, each of which has a certain delay time. A delay time is determined by selecting the number of inverters serially connected in the delay circuit. However, the transmission delay times in the CMOS circuits are subject to surrounding temperature changes or voltage changes, which decreases the accuracy of the delay times in the semiconductor test system. Therefore, to maintain the accuracy or to stabilize the delay times in the semiconductor test system, the following methods or technologies are used in the conventional delay circuits having the CMOS gates as delay elements.
In one conventional method, a heater is provided in an LSI (large scale integrated) circuit having CMOS gate delay circuits. The heater is positioned close to the CMOS gate delay circuits in the LSI. A delay time detector is also provided in the LSI circuit or in the close proximity of the LSI circuit to detect the delay time changes in the CMOS gate delay circuits. Since the delay times in the CMOS gates vary on the changes of the surrounding temperature, the heater is controlled to maintain the delay times of the CMOS gates constant based on the detected delay time changes.
However, in this conventional method, an overall power consumption in the LSI circuit increases since the additional power is consumed to raise the internal temperature of the LSI circuit. Namely, to maintain the constant delay time, electric currents must be provided to the heater so as to control the internal temperature and thus the delay times in the CMOS delay circuit. Thus, it is not possible to decrease the power consumption in the LSI circuit. Further, additional circuit components are inevitable such as semiconductor cells to be used as the heater and the delay time detector.
In the other conventional method, an overall number of pulses or total frequencies in the delay circuit is controlled to be constant. Since the heat generation by the CMOS gates is proportional to the number of pulses (changes of state in the CMOS gates) or the overall frequency provided to the CMOS gates, it is attempted to maintain the temperature of the CMOS gate delay circuit constant by controlling the overall pulses in the delay circuit constant.
For so doing, a dummy circuit formed of CMOS gates is provided in the LSI circuit to receives the number of pulses to supplement the pulses short in the actual CMOS delay circuit to make the overall number of pulses to be equal to the predetermined value. For example, in case where the predetermined overall number of pulses in one second is 20,000.000 and the actual number of pulses provided to the CMOS gate delay circuit is 12,000,000 to form a specific test signal, 8,000,000 pulses are generated to be provided to the dummy CMOS circuit.
However, in this conventional method, as in the first example, the overall power consumption in the LSI circuit increases since the additional power is consumed to operate the supplemental number of pulses in the dummy CMOS circuit to make the overall number of pulses in the LSI circuit constant. Namely, to maintain the constant delay time, additional pulses must be provided to the dummy circuit so as to control overall number of pulses constant. This is because to control the overall number of pulses constant is to control the internal temperature and thus the delay times in the CMOS delay circuit constant.
Thus, in this example, it is not possible to decrease the power consumption in the LSI circuit since the additional power consumption is always necessary to stabilize the delay times. Further, additional circuit components are inevitable such as, in addition to the dummy CMOS circuit as mentioned above, a circuit for detecting the number of pulses provided to the CMOS delay circuit and a circuit which generates the supplemental number of pulses for the dummy circuit.
In the further method, source voltages to the CMOS gates delay circuit are controlled to stabilize the delay time of the delay circuit. As noted above, the delay times in the CMOS gates vary depending on the source voltages supplied to the CMOS gates. Thus, the delay times in the CMOS gates are monitored and a control voltage is feedbacked to adjust the source voltages to the CMOS gates to control the delay times constant.
In this method, however, as in the above two examples, the power consumption in the semiconductor test system increases. This is because the control of the voltage sources must involve voltage drops in a source voltage generating circuit and thus the source voltages must be larger than an ordinary source voltage level to secure a certain control voltage range.
Furthermore, in this method of controlling the source voltages to the CMOS gates, since the delay time change by the change of the source voltage is small, an additional control means is usually necessary to compensate the delay time variance between each CMOS gates. For example, to maintain the delay time of the CMOS gates constant, an output capacitance of each of some of the CMOS gates must also be controlled in addition to the control of the source voltages. Therefore, the number of circuit components or an overall circuit size increases in this example.
Moreover, in all of the above three conventional examples, although the delay times can be controlled to be constant, it is not possible to control a very small amount of delay time for each CMOS gate.